1. Field of the Invention
This invention relates generally to a method for producing a mask ROM and, more particularly, to an improved method for manufacturing the memory cell array portion and a mask ROM produced by this method.
2. Description of the Background Art
Memory integrated circuits currently in use may be roughly classified according to their writing function into a read/write memory or RWM in which not only readout but also free writing may be made after completion of manufacture, and a read only memory or ROM in which writing cannot be made and which is used only for readout after completion of manufacture. The ROM is used for storage of fixed information, such as character patterns, since the information stored therein remains unerased after power is turned off. The ROM may be further classified into an erasable and programmable ROM or EPROM in which the stored information can be modified electrically after completion of manufacture and in which the stored information can be erased by, for example, irradiation of ultraviolet rays, and a mask ROM in which the information is written in the course of manufacture and the stored information cannot be modified after completion of manufacture. The mask ROM is employed for storage of fixed data such as character patterns in a CRT display or the BASIC program for a personal computer.
The memory part of the currently commercialized mask ROM includes in general a large number of MOS transistors arranged in a matrix configuration. Each of these MOS transistors is used as a memory cell. When a MOS transistor is formed on a semiconductor substrate, it becomes necessary to provide three regions, that is, source, drain and gate regions. It is necessary for the size of each of these three regions to be large enough to achieve the function as the MOS transistor; so that it cannot be reduced in size infinitesimally. Hence, despite the recent demand for miniaturization of semiconductor integrated circuit devices, there are naturally imposed limitations on miniaturization of the area of the memory part in its entirety, as long as MOS transistors are used as the memory cells. This problem becomes most serious particularly with increase in the storage capacity of the mask ROM. On the other hand, the demand for a larger memory capacity of the IC memory inclusive of the mask ROM has become more remarkable in recent years. Thus an improved mask ROM has already been proposed for meeting the contradictory demands for miniaturization of a variety of semiconductor integrated devices, inclusive of IC memories, and the larger storage capacities of the IC memories. In such an improved mask ROM, a device or element having a diode construction is used as a memory cell in place of a device or element having a MOS transistor configuration.
FIGS. 6A to 6C show the structure of a memory cell array of an improved mask ROM disclosed in the Japanese Patent Publication No. 61-1904. FIG. 6A is a plan view of the memory cell array and FIGS. 6B and 6C are cross sectional views taken along dotted lines (a) and (b) of FIG. 6A, respectively. Referring to these figures, this memory cell array is formed on a monocrystalline silicon semiconductor substrate 40. An insulating film 48 formed by a silicon oxide film, is formed on the surface of the substrate 40. A large number of band-like N-type polysilicon layers 42 are formed in parallel with one another on this substrate 40. An insulating layer 41 is formed on the overall surface of the semiconductor substrate 40, inclusive of the polysilicon layers 42, and openings or contact holes 44 are selectively formed in the insulating layer 41. P-type polysilicon regions 45 are formed by introducing impurities into the polysilicon layers 42 below these contact holes 44. A large number of parallel band-like electrically conductive layers 43 are formed on the insulating layer 41 and on the contact holes 44 for intersecting the polysilicon layers 42. These contact holes 44 are selectively formed at the points of intersection of the polysilicon layers 42 and the electrically conductive layers 43. Each of the band-like polysilicon layers 42 corresponds to each word line and each of the band-like electrically conductive layers 43 corresponds to each bit line.
As may be seen from FIG. 6A, the points of intersection between the band-like polysilicon layers 42 and the band-like electrically conductive layers form a matrix. Referring to FIGS. 6B and 6C, pn junctions are formed in the polysilicon layers 42 below the contact holes 44 only at those points of intersection associated with the contact holes 44. Therefore, when a forward voltage is applied to the electrically conductive layers 43 having the points of intersection associated with the contact holes 44, the current flows in the associated polysilicon layers 42. On the other hand, when a forward voltage is applied to the electrically conductive layers 43 having the points of intersection not associated with the contact holes 44, no current flows through the polysilicon layers 42 at those points of intersection, since the electrically conductive layers 43 and the polysilicon layers 42 are insulated from each other by the insulating layer 41. Therefore, when a bit line is selected, a predetermined voltage is applied to this bit line and a word line is then selected and checked as to whether or not the current flows in this word line, it can be checked whether or not a contact hole is provided at the point of intersection between the electrically conductive layer 43 associated with the selected bit line and the polysilicon layer 42 associated with the selected word line. Therefore, in the manufacture of the memory cell array of the mask ROM, when the presence or the absence of the contact holes is associated with the logical value "1" or "0", and the formation pattern of the contact holes is selected in dependence upon the information to be stored in the mask ROM, it becomes possible to read out the stored information from the mask ROM after completion of manufacture, as in the conventional device. That is, a single MOS transistor is not used as a memory cell, as a conventional art but simply a pn junction, that is, a diode, is used as the memory cell. Hence, the area required for a memory cell is determined by the widths of the polysilicon layer 42 and the electrically conductive layer 43. The minimum values of the widths of the electrically conductive layers 43 and the polysilicon layers 42 are determined by the limit line-and-space value in the current manufacture technique. Therefore, by reducing these widths, the area occupied by each memory cell on the substrate may be markedly lesser than that of the conventional device, so long as contact holes 44 can be provided. Thus a mask ROM can be provided which is significantly lesser in size than the conventional mask ROM in which a MOS transistor is used as a memory cell.
The process for production of the memory cell array shown in FIG. 6 is explained. First, an oxide film is formed such as by selective oxidation on a monocrystalline silicon substrate on which the memory cell array is to be formed. In this manner, a monocrystalline silicon substrate 40 having an insulating surface layer is formed. A large number of band-like polysilicon layers are formed in parallel to one another on this insulating film. Meanwhile, polysilicon is an intrinsic semiconductor, its conductivity type being neither an N-type or a P-type. Therefore, for rendering the polysilicon layer into an N-type, N-type impurities are introduced into this polysilicon layer. In this manner, a large number of parallel band-like N-type polysilicon layers 42 are produced. An insulating layer 41 is then formed on the overall surface of the substrate 40 inclusive of the surfaces of the N-type polysilicon layers 42. Then, contact holes 44 are formed such as by etching selectively on the insulating layer 41, in dependence upon the information desired to be stored in the mask ROM. Then, P-type impurities are introduced selectively by ion implantation into those regions of the N-type polysilicon layers 42 in which the contact holes 44 are provided. In this manner, P-type polysilicon regions 45 are formed at those portions of the N-type polysilicon layers 42 in which the contact holes 44 are provided. Finally, a large number of parallel band-like electrically conductive layers 43 are formed from, for example, aluminum, on the insulating layer 42 inclusive of the contact holes 44.
The actual manufacture process of the mask ROM chip having the above described memory cell array is hereinafter explained. FIG. 7 is a flowchart showing the outline of the manufacture process for the mask ROM chip. Referring to this figure, a region or an island of a conductivity type opposite to the conductivity type of a monocrystalline silicon substrate is formed on the monocrystalline silicon substrate. This region may prove to be a region on which the source and drain of the transistor are to be formed in the subsequent process. The substrate is then selectively oxidized for forming a thick insulating film of a field oxidation film for isolating adjacent circuit devices or elements from one another. The polysilicon layers that are to be the gate of the P-channel transistor and the N-channel transistor to be used as the peripheral circuits of the memory cell array and that are to be the word lines of the memory cell array are then formed. The polysilicon layers that are to be the word lines are rendered at this time into the N-type by introducing N-type impurities into these polysilicon layers. The source and the drain regions of the N-channel and P-channel transistors are then formed by selectively introducing impurities onto the substrate surface. An insulating film is then formed on the overall surface of the substrate for smoothing the irregularities on the substrate. This is referred to FIG. 7 as "formation of smooth coat film". Contact holes are then formed selectively in this insulating film. Then, P-type impurities are introduced by ion implantation through these contact holes into the polysilicon layers that are to be the word lines of the memory cell array. This is referred to FIG. 7 as "implantation". In this manner, pn junctions are formed only in the memory cells provided with the contact holes. Then, electrically conductive layers are formed on the substrate inclusive of the contact holes in accordance with the desired wiring pattern. Finally, a glass layer is formed as a protective layer for device protection.
As long as the manufacture process is concerned, the above described mask ROM having a memory cell array making use of a single pn junction as a memory cell presents the following disadvantages.
The manufacture process of the memory cell array part includes the step of introducing N-type impurities into the polysilicon layer for rendering the polysilicon layer into an N-type, and the step of introducing P-type impurities by ion implantation into the regions of the N-type polysilicon layers provided with the contact holes for rendering these regions into the P-type. When impurities are introduced into the polysilicon which is neither of the N nor of the P conductivity type, for rendering the polysilicon into an N-type, impurities are introduced at a concentration of the order of 10.sup.14 .about.10.sup.16 /cm.sup.2. On the other hand, when the polysilicon once rendered into the N-type is to be converted into the P-type opposite thereto, impurities are introduced at a concentration of the order of 10.sup.18 .about.10.sup.20 /cm.sup.2 which is higher than in the case of rendering the polysilicon which is neither of the P-type nor of the N-type into the N-type, since it is necessary to reverse the polarity of the polysilicon once doped with the N-type impurities by introducing P-type impurities into polysilicon. Meanwhile, polysilicon is not formed by homogeneous single crystals, but is an aggregate of particulate materials called grains. FIG. 9 shows the construction of polysilicon highly schematically. In this figure, each of the particles 82 represents each grain making up polysilicon. The state of distribution of impurities introduced into the above described polysilicon structure is not so uniform as in the case of introducing the impurities into the monocrystalline silicon. FIG. 10 shows the state of diffusion of the P-type impurities introduced into the N-type polysilicon, herein thought of as a grain, for rendering the N-type polysilicon into the P-type. It may be seen from this figure that the P-type impurities are diffused from the outside towards the interior of the grain. Therefore, when it is assumed that the grain is rendered uniformly to the N type to its innermost region, those portions of the grain, shown by hatching in the figure, in which the concentration of the P-type impurities is high enough to render the N-type polysilicon into the P-type, are rendered into the P-type, while that portion, shown at near the center of the grain, in which the concentration of the P-type impurities is not so high, remains to be of the N-type. Hence, the polysilicon once rendered into the N-type can not be rendered uniformly into the P-type. Meanwhile, when impurities are introduced into the polysilicon which is neither of the P-type or nor of the N-type to render the polysilicon into the N-type, the above described properties of polysilicon present no particular problems. It is because those regions of the polysilicon doped with impurities are rendered into the N-type in their entirety even if the state of distribution of the impurities in polysilicon, that is, the state of rendering into the N-type of polysilicon, differ slightly with respect to each of the grains.
As described hereinabove, it is difficult to render the polysilicon, once rendered into the N-type, uniformly into the P-type on the grain level. Therefore, when the N-type polysilicon is rendered into the P-type, there is no definite boundary between the region which has been turned into the P-type and the region which remains to be of the N-type. This means that the pn junction, which is most critical as a memory cell, can hardly be formed. Even assuming that the pn junction that may play the role of the diode, that is, the role of the memory cell, the problem of extremely low reverse voltage is still presented because the voltage withstand properties of the pn junction remains markedly inferior to that of the monocrystalline silicon. In this manner, it is difficult to produce a desirable pn junction by the conventional manufacture methods.
On the other hand, the following constraints are imposed when forming the P-type region in the N-type polysilicon layers that are to be the future word lines. FIGS. 8A and 8B are sectional views of a memory cell having a contact hole. FIGS. 8A and 8B show the P-type regions 45 formed in the N-type polysilicon layers to a deeper and shallower thickness along the direction of the thickness of the N-type polysilicon layer respectively. It is noted that the N-type polysilicon layer 42 is extended in a direction normal to the plane of the drawing sheet. Meanwhile, depending on the presence or absence of the contact hole in the selected memory cell, it is necessary for a sufficient amount of current to flow in the word line corresponding to the memory cell. To this end, a lesser value of the resistance of the word line is preferred. The resistance value of the word line is influenced by the cross-sectional area of the N-type polysilicon layer 42. On the other hand, a partially electrically conductive P-type polysilicon region 45 is formed in the N-type polysilicon layer 42 that is to be the future word line. Therefore, in the region in which the P-type region 45 is formed, that is, in the region below the contact hole, the effective cross sectional area of the N-type polysilicon layer 42 through which the current flows actually is equal to the design cross sectional area a.times.h, wherein h and a designate the thickness of the N-type polysilicon layer 42 and its width, respectively, less the cross-sectional area of the P-type polysilicon region 45, that is, d.times.b, wherein d and b designate the thickness and width of the P-type polysilicon region 45, respectively. Therefore, for reducing the resistance value of the word line, the lesser sectional area of the P-type polysilicon region is preferred (see FIGS. 8A and 8B). That is, the lesser values of the thickness d and width b of the P-type polysilicon region 45 are preferred. However, reducing the width c of the contact hole means increasing the contact resistance value between the conductor layer 43 and the N-type polysilicon layer 42, since the width b of the P-type polysilicon region 45 is thought to be about equal to the width c of the contact hole c. On the other hand, if the thickness d of the P-type polysilicon region 45 is too small, the formed pn junction does not play the role of the memory cell. Therefore, when forming the P-type region 45 in the N-type polysilicon layer 42, it is necessary to introduce impurities to a moderate depth in consideration of the above described constraints. On the other hand, the desirable pn junctions can hardly be produced by the conventional manufacture methods, as described hereinabove. Therefore, in consideration of the above constraints, it is extremely difficult to produce the P-type polysilicon region 45 to a suitable depth. For example, when forming the P-type polysilicon region 45, the amount of the P-type impurities to be introduced by ion implantation is increased with a view to raising the concentration of the impurities to produce a sufficiently satisfactory pn junction, it becomes difficult to control the region of implantation. On the other hand, when the energy of ion implantation is increased with a view to increasing the depth of the P-type polysilicon region 45 to some extent, there is a risk that the N-type polysilicon layer 42, the interlayer film 48 or even the substrate 40 may be injured.
In addition, the N-type polysilicon is rendered into the P-type under the conditions of ion implantation such as the energy for ion implantation and the amount of ions to be implanted, which are different from those when the N-type monocrystalline silicon is rendered into the P-type. As a result, the process of producing a mask ROM chip including a memory cell array and any peripheral circuit on the same substrate containing field effect transistors becomes complicated. That is, the step of forming a pn junction at the portion of the word line which is to be the future memory cell and the step of forming source and drain regions of the transistor must be separated from each other, because the source and drain regions of the P-channel transistor are produced by introducing P-type impurities by ion implantation into N-type regions of the monocrystalline silicon substrate while the memory cells are formed by introducing P-type impurities into regions of N-type polysilicon thereby forming two kinds of P-type regions in the N-type region. For this reason, the step of forming the pn junction in the memory cell is necessarily additionally required near the last step in the manufacture process for the mask ROM.
As described hereinabove, the mask ROM employing a single pn junction as a memory cell as shown in FIG. 6A presents various manufacture problems and hence cannot be provided as commercial products without considerable difficulties.